A key metric for performance of transistors is the on-current, which is the current of a transistor per unit gate width when it is turned on. The minority carrier mobility has been identified as a limiting factor in determining the on-current of high performance transistors. One of the key parameters determining the mobility of minority carriers is the crystallographic surface orientation on which the channel of the transistor is formed. By manipulating the transistor structure such that a favorable surface orientation is used for each type of transistors, both P-type field effect transistors (PFETs) and N-type field effect transistors (NFETs) with high minority carrier mobility may be formed in a CMOS transistor circuit.
In some semiconductors, electron mobility and hole mobility achieve maximum on different crystallographic planes. For example, electron mobility achieves the maximum in the {100} surface orientations and the minimum in the {110} surface orientations within single crystal silicon. In contrast, hole mobility achieves the maximum in the {110} surface orientations and the minimum in the {100} surface orientations within single crystal silicon.
The prior art has shown that the performance of a semiconductor circuit can be enhanced by utilizing different crystallographic planes for the PFET and NFET devices. The use of two different surface orientations on the same semiconductor substrate is called “hybrid orientation technology (HOT)” in the semiconductor industry. The prior art also provides methods of implementation of the hybrid orientation technology.
According to an approach in hybrid orientation technology, two different crystallographic planes are provided by bonding two or more wafers. In some cases, epitaxy in conjunction with chemical mechanical planarization (CMP) is employed to create areas with different surface orientations. The topography of surfaces after the bonding, epitaxy, and CMP tend to be planar. However, disadvantages of this approach include the complexity of the processes and the propensity of epitaxy for defect generation. Furthermore, a substantial portion of the surface area around the boundary between two different crystallographic orientations becomes unusable for high performance CMOS devices due to crystalline defects at the boundary of the single crystal area. This limits the flexibility in the layout of the CMOS circuitry since PFETs and FETs need to be placed within close proximity of each other for many high performance circuit designs.
A different approach utilizing facets with different crystallographic orientations than the original surface of a semiconductor substrate is known in the prior art. As an example, Weber et al., “A Novel Locally Engineered (111) V-channel pMOSFET Architecture with Improved Drivability Characteristics for Low-Standby power (LSTP) CMOS Applications,” 2005 Symposium on VLSI, 2005, pp. 156-157, discloses a transistor structure in which a channel is formed within a V-shaped groove. The current flows within the plane of the V-shape groove following the path in the shape of the letter, V, including an inflection in the direction of the current in the middle of the channel.
Also, methods of forming a V-shaped groove with different crystallographic orientations than that of the original substrate by patterning a rectangular area of the semiconductor surface for exposure to a wet etch is also known. However, the methods of forming such V-shaped grooves according to the prior art involves lithographic patterning of the semiconductor area to be exposed to an etch. In other words, a lithographic mask must contain the patterns corresponding to the outer edges of the V-shaped grooves. Since lithographic processes require a certain level of overlay tolerance, the silicon area within which a V-shaped groove is to be formed must be larger than the size of the V-shaped groove. Thus, the silicon area needs to include an “overlay budget,” or an extra space of silicon area to allow for the variations in the overlay during a lithographic process. However, each generation of semiconductor technology requires more compact transistor designs that use less of the silicon area for a transistor.
Therefore, there exists a need for a structure and methods for a more compact transistor with a V-shaped groove containing crystallographic facets formed on a semiconductor substrate.
Furthermore, there exists a need for a CMOS transistor structure and methods of forming a compact transistor with a V-shaped groove containing crystallographic facets formed on a semiconductor substrate along with another transistor with a channel formed on a semiconductor surface with the substrate orientation.